datasheet high performance communication buffer ics91305i idt? high performance communication buffer 1 ics91305i rev g 090612 description the ics91305i is a high performance, low skew, low jitter clock driver. it uses a phase lock loop (pll) technology to align, in both phase and frequency, the ref input with the clkout signal. it is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 mhz. ics91305i is a zero delay buffer that provides synchronization between the input and output. the synchronization is established via clkout feed back to the input of the pll. since the skew between the input and output is less than +/- 350 ps, the part acts as a zero delay buffer. the ics91305i comes in an eight pin 150 mil soic package. it has five output clocks. in the absence of ref input, will be in the power down mode. in this mode, the pll is turned off and the output buffers are pulled low. power down mode provides the lowest power consumption for a standby condition. features ? zero input - output delay ? frequency range 10 - 133 mhz (3.3v) ? 5v tolerant input ref ? high loop filter bandwidth ideal for spread spectrum applications ? less than 200 ps jitter between outputs ? skew controlled outputs ? skew less than 250 ps between outputs ? available in 8 pin 150 mil soic & 173 mil tssop packages ? 3.3v 10% operation ? supports industrial temperature range -40c to 85c block diagram
ics91305i high performance co mmunication buffer idt? high performance communication buffer 2 ics91305i rev g 090612 pin configuration pin descriptions
ics91305i high performance co mmunication buffer idt? high performance communication buffer 3 ics91305i rev g 090612 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics91305i. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristics at 3.3v notes: 1.guaranteed by design and characterization. not subject to 100% test. 2.all skew specifications are mesured with a 50 transmission line, load teminated with 50 to 1.4v. 3.duty cycle measured at 1.4v. 4.skew measured at 1.4v on rising edges. loading must be equal on outputs. dc characteristics parameter symbol test conditions min typ max units input low voltage v il 0.8 v input high voltage v ih 2.0 v input low current i il v in =0v 19 100.0 a input high current i ih v in =v dd 0.10 250.0 a output low voltage 1 v ol i ol = 12ma 0.25 0.4 v output high voltage 1 v oh i oh = -12ma 2.4 2.9 v power down supply current i dd ref = 0 mhz 0.3 100.0 a supply current i dd unloaded oututs at 66.66 mhz sel inputs at v dd or gnd 30.0 80.0 ma
ics91305i high performance co mmunication buffer idt? high performance communication buffer 4 ics91305i rev g 090612 switching characteristics notes: 1. guaranteed by design and characte rization. not subject to 100% test. 2. ref input has a threshold voltage of 1.4v 3. all parameters expected with loaded outputs parameter symbol condition min typ max units output period t1 with cl=30pf 100.00 (10) 7.5 (133) ns (mhz) input period t1 with cl=30pf 100.00 (10) 7.5 (133) ns (mhz) duty cycle 1 dt1 measured at 1.4v; cl=30pf 40.0 50 60 % duty cycle 1 dt2 measured at vdd/2 fout <66.6mhz 45 50 55 % rise time 1 tr1 measured between 0.8v and 2.0v: cl=30pf 1.2 1.5 ns fall time 1 tf1 measured between 2.0v and 0.8v; cl=30pf 1.2 1.5 ns delay, ref rising edge to clkout rising edge 1, 2 dr1 measured at 1.4v 0 350 ps output to output skew 1 tskew all outputs equally loaded, cl=20pf 250 ps device to device skew 1 tdsk-tdsk measured at vdd/2 on the clkout pins of devices 0 700 ps cycle to cycle jitter 1 tcyc-tcyc measured at 66.66 mhz, loaded outputs 200 ps pll lock time 1 t lock stable power supply, valid clock presented on ref pin 1.0 ms jitter; absolute jitter 1 tjabs @ 10,000 cycles c l = 30pf -200 70 200 ps jitter; 1 - sigma 1 tj1s @ 10,000 cycles c l = 30pf 14 60 ps
ics91305i high performance co mmunication buffer idt? high performance communication buffer 5 ics91305i rev g 090612 output to output skew the skew between clkout and the clk(1-4) outputs is not dynamically adjusted by the pll. since clkout is one of the inputs to the pll, zero phase difference is maintained from ref to clkout. if all outputs are equally loaded, zero phase difference will maintained from ref to all outputs. if applications requiring zero output-output skew, all the outputs must equally loaded. if the clk(1-4) outputs are less loaded than clkout, clk(1-4) outputs will lead it; and if the clk(1-4) is more loaded than clkout, clk(1-4) will lag the clkout. since the clkout and the clk(1-4) outputs are identical, they a ll start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. timing diagrams with different loading configurations
ics91305i high performance co mmunication buffer idt? high performance communication buffer 6 ics91305i rev g 090612 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 0 8 0 8
ics91305i high performance co mmunication buffer idt? high performance communication buffer 7 ics91305i rev g 090612 package outline and package dimensions (8-pin tssop, 4.4 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 91305amilf 305amilf tubes 8-pin soic -40 to +85 c 91305AMILFT 305amilf tape and reel 8-pin soic -40 to +85 c 91305agilf 305il tubes 8-pin tssop -40 to +85 c 91305agilft 305il tape and reel 8-pin tssop -40 to +85 c index area 1 2 8 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l millimeters inches symbol minmaxminmax a -- 1.20 -- 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 2.90 3.10 0.114 0.122 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa - 0.10 - 0.004
ics91305i high performance co mmunication buffer idt? high performance communication buffer 8 ics91305i rev g 090612 revision history rev. originator date description of change g d. chan 09/06/12 1. updated ordering information to inlclude ?i? for industrial temp range in ordering scheme. 2. re-created datasheet in latest template.
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